1. Field of the Invention
This invention relates to new and improved charge redistribution circuitry for pulse code modulation encoding and, in particular, to such circuitry for use in apparatus for encoding voice in a companded code to maximize signal-to-noise performance. Accordingly, it is a general object of this invention to provide a new and improved circuit of such character.
2. Description of the Prior Art
Voice signals can be coded in a nonlinear digital code for digital telephone transmission in order to maintain a high ratio of signal-to-noise over a wide range without requiring excessive digital transmission bandwidth. One widely used code in the United States is the 15 segment approximation of the .mu.=255 compression law. An analog signal, such as speech, can be converted into a digital coded output using an 8-bit pulse code modulation format in which, in each of the 15 segments, there are 16 equal steps, with the exception of the segment passing through the origin which contains 31 equal steps. In such case, a standard sampling rate for voice signals is 8 KHz, resulting in a 64 kilobits PCM signal.
Coders implementing such code have been relatively complex. For economic reasons, the coder/decoder (codec) is often shared over 24 or more channels through the use of analog multiplexers at the input and output. However, in many cases, a low cost codec per channel offers advantages. Recognition thereof has led to extensive studies of alternative codes, particularly linear and adaptive delta modulation which allow particularly simple codec hardware implementations. Drawbacks to delta modulation are its incompatability with standard PCM, and poor performance for data transmission.
A .mu.255 PCM voice encoder which is amenable to onchip monolithic realization in standard MOS technology has been proposed in the prior art. Such a coder includes some elements found in linear A/D converters suggested by others. The prior art encoder includes two binary-weighted capacitor arrays as the key precision elements. Other elements include a binary comparator, a near unity gain buffer amplifier with very high input impedance, a reference source V.sub.R, and numerous analog switches. Binary sequencing and control logic totalling about 60 gates and flip-flops and a digital clock are required. A negative reference can be developed by a sub-circuit, so that only a single positive reference is required in the main circuitry. Further description of such a proposed coder is discussed hereinafter following the "Brief Description of the Drawings" under description of a "Prior Art PCM Coder".